1. Field of the Invention
The present invention relates to a method for reducing power consumption in a volatile memory and related device, and more particularly, to a method and related device for eliminating DC current due to wordline to bitline short in the volatile memory operating in a standby mode.
2. Description of the Prior Art
Low power DRAM (dynamic random access memory) design plays an important role in modern electronic devices. There are numerous benefits for using low power designs: battery time can last longer to improve device portability, less energy spending can save cost and conserve natural resources, etc. In a DRAM, standby current is a current level consumed by the DRAM in a standby state (or quiescent state). According to JEDEC, the Joint Electronic Device Engineering Council, for example, an upper limit of the standby current (Idd6) should be in the range of 500 uA, which has become a highly challenging design task. Among numerous factors obstructing the way to meet low power specifications, wordline to bitline (WL2BL) short, which is also known as cross-fail, is a common defect in DRAM manufacturing process which draws a large portion of DC leakage current. The internal mechanism of leakage current induced by WL2BL short is closely related to the architecture and the memory access functions of the DRAM. The memory refresh, memory read, or memory write procedures in DRAM device can be initiated with a memory refresh command, a memory read command or a memory write command, respectively. The executions of these commands start with a selected wordline with voltage VWL being driven on to ON state voltage (VPP) produced by a built-in charge pump circuit on the memory device, the data transistors corresponding to the wordline are switched on altogether and the charges in the selected memory cell capacitors are then transferred onto the bitlines. Please refer to FIG. 1, which illustrates a bitline array structure 10 of a DRAM. The bitline array structure 10 comprises a first bitline array 100, a sense amplifier 102, a second bitline array 104, a first bitline equalizing circuit 106, a second bitline equalizing circuit 108, a sense node activation circuit 110, a first multiplexer 112, a second multiplexer 114 and bitline voltage providers MEQ1, MEQ2. The first and second bitline equalizing circuits 106, 108 coupled to the bitline voltage providers MEQ1, MEQ2 are used to supply equalized voltages to bitlines of the bitline arrays 100, 104. VEQLG is a global signal used to switch the bitline voltage providers MEQ1, MEQ2, and with VEQLG signal high, the equalizing voltage VBLEQ is made to supply to every bitlines in the DRAM. For clearly explaining the operations of the bitline arrays 100, 104 and the sense amplifier 102, please refer to FIG. 2. FIG. 2 illustrates an implementation of the bitline array structure 10 shown in FIG. 1 according to the prior art. The circuit components in the first bitline array 100, the sense amplifier 102, the first bitline equalizing circuit 106, and the sense node activation circuit 110 are shown together for clear explanation. The first bitline array 100 comprises an example memory cell transistor M1 and a memory cell capacitor C1. First, the bitline of the first bitline array 100 has been precharged to a mid-level of voltage named bitline equalizing voltage (VBLEQ). When the wordline with on state voltage switches on the memory cell transistor M1, the charges from the memory cell capacitor C1 will generate small voltage differences on the bitline of the first bitline array 100. The small voltage perturbation deviated from the equalizing voltage VBLEQ makes bitline's voltage level moved somewhat positively or negatively from VBLEQ, and the small voltage deviation is magnified by the sense amplifier 102. The sense amplifier 102 comprises an n-latch composed of two NMOS transistors MN1, MN2, and a p-latch composed of two PMOS transistors MP1, MP2. The sense amplifier 102 is designed to work as a bi-stable memory device whose initial state is a mid-level voltage (VBLEQ) and the final stabilized state is either a high voltage state or a low voltage state, depending on the voltage of the bitline. The function of the sense amplifier 102 is also controlled by the sense node activation circuit 110, which is used to activate the sense amplifier 102. The sense node activation circuit 110, composed of NMOS transistors MAN1 to MAN5, and PMOS transistor MAP1, is designed to activate the sense amplifier 102 after the memory cell capacitor C1 is switched on and the charges in the capacitor C1 starts affecting the voltage level of the bitline of the first bitline array 100. The sense node activation circuit 110 will help the sense amplifier 102 to amplify the small deviation of the bitline's voltage to become one of two final states. In case of the operation of a memory refresh command, the final state of the sense amplifier 102 are written back to the original memory cell capacitor C1, and the wordline voltage dropped back to the off state voltage (VNWL) to complete the memory refresh command. The memory read command differs from the memory refresh command by further transferring the final state of the sense amplifier 102 to the external circuitry. The memory write command applies an external voltage to overwrite the state in the sense amplifier 102 as well as the memory cell capacitor C1.
Please refer to FIG. 3, which illustrates the bitline array structure 10 with a WL2BL short defect. The WL2BL short defect refers to a wordline WL and a bitline array (the first bitline array 100 in this example) exhibits a finite electrical resistance RS between the wordline and the bitline array owing to manufacturing fault. The defect is usually a very small electrical resistive short between the bitline contact and the wordline poly via the sidewall spacer. The existence of WL2BL short increases the operating power of the DRAM chip owing to extra leakage current.
According to the experiment, while operating in the standby mode, the WL2BL short defect will draw leakage currents from the voltage VBLEQ to the voltage VNWL (wordline off state voltage). Please refer to FIG. 4A to FIG. 4C. FIG. 4A to FIG. 4C illustrate circuit diagrams showing three different leakage paths from VBLEQ to VNWL which are marked with dashed arrow lines:
Path 1, via the bitline voltage provider MEQ1 corresponding to the bitline equalizing circuit 106 of the defect bitline array 100 to the wordline WL with off-state voltage;
Path 2, via the sense node activation circuit 110 through the n-latch transistors MN1, MN2 of the sense amplifier 102 to the wordline WL with off-state voltage; and
Path 3, via the sense node activation circuit 110 through the p-latch transistors MP1, MP2 of the sense amplifier 102 to the wordline WL with off-state voltage.
According to the prior art, for DRAM with WL2BL short defect and in the standby state, the bitline voltage provider MEQ1 remains on. Because the gate terminal of the bitline voltage provider MEQ1 is connected to the global signal VEQLG, and according to the prior art, there is no way to switch off a specific MEQ1 to stop the leakage current via Path 1. Meanwhile, according to the prior art, there is no way to stop the leakage current via Path 2 and Path 3, because the multiplexers 112, 114 are switched on during the standby state. Since the multiplexers 112, 114 are controlled by global signals VMUX1 and VMUX2, respectively, there is no way to solely turn off any specific multiplexer. For example, if the WL2BL defect happens in the first bitline 100, the gate of the bitline voltage provider MEQ1 is connected to the global signal VEQLG, the gates of transistors (MUXN1, MUXN2) of the first multiplexer 112 are connected to the global control signal VMUX1, and can't be switched off during standby state. All three leakage paths (Path 1, Path 2 and Path 3) remain conducting for leakage current.
Furthermore, since the wordline off-state voltage (VNWL) is generated by an on-chip charge pump circuit. The inherent inefficiency of the charge pump circuit in the wordline circuit magnifies the leakage current, and adds substantial current level to the external voltage source. According to the prior art, while no adequate measures are available for reducing the leakage current both in the standby mode, the leakage current resulting from WL2BL short defect of DRAM is too large to be accepted and the upper limits set for Idd6 could be unwillingly surpassed.